Collaborating with US and Japanese material and equipment manufacturers in Silicon Valley to deliver the best solutions for advanced semiconductor packaging

Tokyo – TOPPAN Inc. (TOPPAN), a TOPPAN Group company and wholly owned subsidiary of TOPPAN Holdings Inc., has announced its participation in US-JOINT1 from November 18. US-JOINT is a US-Japan consortium for next-generation semiconductor packaging established in July this year and spearheaded by Resonac Corporation (Resonac), a leading manufacturer of semiconductor back-end process materials. TOPPAN will participate as a packaging substrate manufacturer and aim to contribute to the evolution of next-generation semiconductor packaging technology through involvement in the development of mounting technologies and the creation of a next-generation packaging evaluation platform in the US.

Background and objectives

Next-generation semiconductors are expanding rapidly for generative AI and autonomous driving, requiring increasingly complex semiconductor packaging structures, such as 2.5D and 3D,2 that are in turn driving an increase in the types of materials used. In recent years, leading fabless semiconductor manufacturers and major tech companies have intensified efforts to design and develop semiconductors in-house, particularly in the US. This is prompting a need for accelerated co-creation and close cooperation from locations that are closer to customers.

Led by Resonac and based in Silicon Valley, US-JOINT brings together ten of the leading material and equipment manufacturers from the US and Japan as a co-creation platform for development of semiconductor packaging technology.

By participating in US-JOINT, TOPPAN will leverage its technical development capabilities for high-end packaging substrates and help resolve challenges in advanced semiconductor packaging technologies that are of high interest to customers. By doing so, TOPPAN aims to spur the creation of new business opportunities and strengthen its semiconductor packaging substrate business.

Future activities

US-JOINT’s activities will be based at a new facility in Silicon Valley. The construction of clean rooms and installation of equipment will begin this year, and the facility is expected to be fully operational in 2025. Prototype lines will be used for research and development of cutting-edge back-end processing, such as chip mounting, interposers, and packaging substrates. TOPPAN will provide FC-BGA substrates and next-generation semiconductor packaging materials as part of efforts to capture market needs in real time and accelerate research and development of back-end process materials and processing technologies.

1. US-JOINT press release from Resonac: https://www.resonac.com/news/2024/07/08/3116.html 
2. 2.5D is a technology for mounting multiple chips onto a silicon substrate called an interposer. 3D is a technology for stacking multiple chips.

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